1. Field of the Invention
The present invention relates to an insulated gate semiconductor device such as an insulated gate bipolar transistor (referred to as an IGBT hereinafter) and a method of fabricating the same.
2. Description of the Background Art
An insulated gate semiconductor device comprises a plurality of p type and n type semiconductor layers alternately joined together in series such that the semiconductor layers at opposite ends are electrically, connected to positive and negative main electrodes, respectively, and at least one of the other semiconductor layers is joined to a gate electrode applying an electric field through an insulator.
&lt;Construction of Background Art Device&gt;
in general, an IGBT comprises a multiplicity of IGBT elements (referred to as IGBT cells hereinafter) connected in parallel. FIG. 32 is a cross sectional view showing a basic structure of an IGBT cell forming the IGBT.
Referring to FIG. 32, a p.sup.+ semiconductor layer 1 is formed of a p type semiconductor substrate and has first and second major surfaces, and an n.sup.+ buffer layer 2 is formed on the first major surface of the p.sup.+ semiconductor layer 1. An n.sup.- semiconductor layer 3 is formed over the n.sup.+ buffer layer 2. In a partial surface region of the n.sup.- semiconductor layer 3 is formed p type base regions 4 by selective diffusion of p type impurities. Further, n.sup.+ emitter regions 5 are formed in a partial region of the p type base regions 4 by selective diffusion of a high concentration of n type impurities. Upper surfaces of the p type base regions 4 between the surface of the n.sup.- semiconductor layer 3 and the surfaces of the n.sup.+ emitter regions 5 serve as channel regions 6. A gate insulation film 7 is formed on the channel regions 6. A gate electrode 8 made of, for example, polycrystalline silicon is formed on the gate insulation film 7.
Emitter electrodes 9 made of, for example, aluminum are formed over the respective upper surfaces of the p type base regions 4 and the n.sup.+ emitter regions 5. The gate electrode 8 and the emitter electrodes 9 are insulated from each other. Gate electrodes 9 for all IGBT cells are electrically connected to each other, and emitter electrodes 9 for all IGBT cells are electrically connected to each other. A collector electrode 10 made of aluminum or the like is formed on the second major surface of the p.sup.+ semiconductor layer 1. The collector electrode 10 is formed integrally for all IGBT cells.
&lt;Operation of Background Art Device&gt;
In operation, a predetermined collector voltage V.sub.CE is initially applied between the emitter electrodes 9 and the collector electrode 10. At this time, when a gate voltage V.sub.GE exceeding a threshold value is applied between the emitter electrodes 9 and the gate electrode 8, the channel regions 6 are inverted into n type, and n type channels are formed in the channel regions 6. Electrons as carriers are emitted from the emitter electrodes 9 through the n type channels into the n.sup.- semiconductor layer 3. The emitted electrons causes forward bias between the p.sup.+ semiconductor layer 1 and the n.sup.- semiconductor layer 3 (including the n.sup.+ buffer layer 2), and holes as carriers are emitted from the p.sup.+ semiconductor layer 1. As a result, the resistance of the n.sup.- semiconductor layer 3 decreases significantly and a collector current I.sub.C flowing from the collector electrode 10 to the emitter electrodes 9 reaches a high value. That is, the IGBT comes into conduction (turns on). The resistance relative to the collector current I.sub.C at this time is represented as an ON resistance. The ON resistance is normally indicated by a saturation collector voltage V.sub.CE (sat) at the time when the collector current I.sub.C has a rated current value. In this manner, the IGBT decreases the resistance of the n.sup.- semiconductor layer 3 by emitting holes from the p.sup.+ semiconductor layer 1 to increase a current-carrying capacity.
Operation of the IGBT from the ON state to the OFF state will be discussed below. Referring again to FIG. 32, when the gate electrode 8 is turned off by zero or reverse-biased gate voltage V.sub.GE applied between the emitter electrodes 9 and the gate electrode 8 in the ON state, the n-type inverted channel regions 6 return to p type, and the emission of electrons from the emitter electrodes 9 stops. No electrons emitted causes the holes to stop being emitted from the p.sup.+ substrate 1. When the electrons and holes left in the n.sup.- semiconductor layer 3 (including the n.sup.+ buffer layer 2) move toward the collector electrode 10 and the emitter electrodes 9, respectively, or disappear by recombination. The holes having a mobility smaller than that of the electrons decrease at lower speeds, and the hole current moving toward the emitter electrodes 9 serves as a tail current.
It will be apparent from the construction of the IGBT of FIG. 32 that the IGBT comprises a parasitic bipolar transistor consisting of the n.sup.+ emitter region 5, the p type base region 4 and the n.sup.- semiconductor layer 3. This parasitic bipolar transistor generally turns on when the hole current flowing in the p type base region 4 exceeds a value. Turning on of the parasitic bipolar transistor causes a parasitic thyristor consisting of the n.sup.+ emitter region 5, the p type base region 4, the n.sup.- semiconductor layer 3, and the p.sup.+ semiconductor layer 1 to turn on (referred to as latch-up of the IGBT). Upon latch-up of the IGBT, the gate voltage V.sub.GE can no longer control the current (collector current I.sub.C) flowing in the IGBT which is then broken down. The breakdown due to latch-up is considered to be liable to occur at specific positions of the IGBT.
FIG. 33 is a plan view of a common IGBT. Referring to FIG. 33, a rectangular gate pad GP is provided in the lower middle of the IGBT. Gate lines GL extend from upper and lower portions of the gate pad GP. The gate line GL from the upper portion extends along the centerline of the IGBT up to a location slightly above the center, and the gate line GL from the lower portion is formed in such a manner as to surround the outer periphery of the IGBT. The emitter electrode 9 is formed in a region enclosed by the central and outer peripheral gate lines GL. IGBT cell regions serving as an active region are indicated by the broken lines of FIG. 33. A p type semiconductor region 11 is formed so as to surround the IGBT cell regions.
FIG. 34 is an enlarged view of a region X enclosed by the dashed-and-dotted lines of FIG. 33, with portions of the emitter electrode 9 removed. Referring to FIG. 34, a multiplicity of IGBT cells are spaced a constant distance W.sub.cel from each other in parallel within a corner portion indicated by the lines C--O--C', each of the IGBT cells including a stripe-shaped contact hole having a width W.sub.ch1. The p type semiconductor region 11 including a stripe-shaped contact hole having the width W.sub.ch1 is formed outside the corner portion shown by the lines C--O--C'. FIG. 35 is a sectional view taken along the line A-A' of FIG. 34, and FIG. 36 is a sectional view taken along the line B-B' thereof.
FIG. 35 illustrates the IGBT cells described with reference to FIG. 32 which are arranged in parallel such that the emitter electrodes 9 are connected to upper surfaces of the p type base regions 4 and n.sup.+ emitter regions 5 of the respective IGBT cells through the contact holes having the width W.sub.ch1. A portion adjacent the side A of FIG. 35 represents a region outside the line C--0 of the corner portion indicated by the lines C--O--C' wherein the p type semiconductor region 11 is formed in the surface of the n.sup.- semiconductor layer 3 by double diffusion in corresponding to the p type base region 4 of the adjacent IGBT cell. The emitter electrode 9 is connected to the upper surface of the p type semiconductor region 11 through the contact hole having the width W.sub.ch1. The p type semiconductor region 11 is much larger than the p type base region 4.
FIG. 36 is a sectional view taken longitudinally of the stripe-shaped contact hole. The p type base region 4 extends in the longitudinal direction of the contact hole, and the emitter electrode 9 extends longitudinally for connection to the p type base region 4. A portion adjacent the side B represents a region outside the line O--C' of the corner portion indicated by the lines C--O--C'. The p type semiconductor region 11 is shown as overlapping the p type base region 4.
Operation of the IGBT having such construction is described when it is on. Holes supplied from the p.sup.+ semiconductor layer 1 directly below the p type semiconductor region 11 pass through a contact hole CH.sub.P on the upper surface of the p type semiconductor region 11 to the emitter electrode 9. However, some of the holes which do not completely pass through the contact hole CH.sub.P flow into the IGBT cell adjacent the p type semiconductor region 11 since the p type semiconductor region 11 is much larger than the p type base region 4. Thus, the IGBT cell adjacent the p type semiconductor region 11 conducts more hole current than other IGBT cells, and the parasitic thyristor consisting of the n.sup.+ emitter region 5, the p type base region 4, the n.sup.- semiconductor layer 3 and the p.sup.+ semiconductor layer 1 turns on as above described to cause latch-up of the IGBT. Then the current (collector current I.sub.C) flowing in the IGBT is not controlled and the IGBT is broken down.
Such a phenomenon often occurs during transition from the ON state to the OFF state. As above stated, turning off of the gate electrode 8 causes electrons to stop being supplied from the emitter electrode 9 to stop the supply of holes from the p.sup.+ semiconductor layer 1. The electrons and holes left in the n.sup.- semiconductor layer 3 (including the n.sup.+ buffer layer 2) move toward the collector electrode 10 and the emitter electrodes 9, respectively. In this case, since the electrons have a great mobility, the holes remain after the electrons pass through to the collector electrode 10. When no electrons are left, the holes which disappear by recombination with electrons in the ON state also move toward the emitter electrodes 9.
The result of quantitative analysis of this phenomenon by computer simulation is shown in FIG. 37. FIG. 37 is a graph showing changes with time in current flowing in the IGBT when the IGBT makes an ON-state to OFF-state transition, the abscissa of the graph being time, the ordinate thereof being current value. Referring to FIG. 37, when the IGBT changes from the ON state to the OFF state, the electron current decreases rapidly during the time interval between 1.98 .mu.sec. and 2.06 .mu.sec., and the hole current increases rapidly from about 2.02 .mu.sec. to provide a more than 1.5.times. increase in hole current. Part of the hole current does not completely pass through the emitter electrodes 9 but flows into the IGBT cell adjacent the p type semiconductor region 11, resulting in latch-up of the IGBT. Hence, the current (collector current I.sub.C) flowing in the IGBT is not controlled and the IGBT is broken down.
Recently, size reduction of IGBT cells has advanced for improvement in IGBT characteristics, and the IGBT cell adjacent the p type semiconductor region 11 has been prone to be broken down for the above mentioned reasons. Relation between size reduction of the IGBT cells and breakdown thereof will be described with reference to FIG. 38. FIG. 38 is an enlarged schematic view of FIG. 35.
Consideration is taken into a carrier density in the ON state. The carrier density is uniform within an IGBT cell as illustrated in FIG. 38. It is assumed that carriers extend at an angle of about 45 degrees from a cell end under the p type semiconductor region 11 as shown in FIG. 38. The thickness of the n.sup.- semiconductor layer 3 is designated as t.sub.n-, the depth of the p type base region 4 of the IGBT cell is designated as P.sub.xj, and the width of the IGBT cell is designated as W.sub.cel. The number of carriers C1 in a region defined by the centerline G of the gate electrode 8 and the centerline S of the IGBT cell is approximately expressed as: EQU C11/2(W.sub.cel .multidot.(t.sub.n- -P.sub.xj)) (1)
Likewise, the number of carriers C2 in a region defined by the centerline G of the gate electrode 8 and the line L.sub.45 indicative of spreading of the carriers is approximately expressed as: EQU C21/2(W.sub.cel .multidot.(t.sub.n- -P.sub.xj))+1/2(t.sub.n- -1/2W.sub.cel).sup.2 (2)
The ratio of C2 to C1 is: ##EQU1## where 1/2W.sub.ch(cel) is the size of a contact hole CH.sub.1 which is provided on the cell and into which current flows by the carriers in the region defined by the centerline G of the gate electrode 8 and the centerline S of the IGBT cell; and W.sub.ch(p) is the size of the contact hole CH.sub.P which is provided on the p type semiconductor region 11 and into which current flows by the carriers in the region defined by the line L.sub.45 indicative of the spreading of the carriers. Expression (3) is arranged into: ##EQU2## Therefore, if the IGBT cell is reduced in size, Expression (4) approximates: ##EQU3## This indicates that when the cell width is less than the thickness of the n.sup.- semiconductor layer 3 due to size reduction of the IGBT cell, more current flows in the contact hole CH.sub.P than in the contact hole CH.sub.1, resulting in a stronger likelihood of IGBT breakdown.
Further, the area of the emitter electrode 9 connected to the p type semiconductor region 11 decreases with size reduction of the IGBT cell, and the holes supplied from the p.sup.+ semiconductor layer 1 directly below the p type semiconductor region 11 are difficult to pass through to the emitter electrode 9. This also results in IGBT breakdown.